Microelectronics, Vol. 2, Pages 3: Development and Optimization of Fine-Pitch RDL for RDL Interposer and Embedded Bridge Die Interposer Fabrication Using Fan-Out Wafer-Level Packaging Technology

Microelectronics doi: 10.3390/microelectronics2010003

Authors:
Jung Won Lee
Sung Hyuk Lee
Jay Kim
Lewis Kang
Han Ju Yu
Min Ji Lee
Seong Hwan Han
Jae Kyung Lee
Hailey Hwang
Jung Gi Kim
Chan Young Hong
Jade Park
Su Hyun Kim
Myeung Jin Kim
Moon Jung Kim

Fine-pitch redistribution layers (RDLs) are key enabling technologies for fan-out wafer-level packaging (FOWLP)-based interposers used in chiplet and high-bandwidth memory (HBM) integration. In this study, a CAR-based photolithography process optimized for fine-pitch RDL fabrication was evaluated to realize 2 μm/2 μm line/space (L/S) RDL structures in an FOWLP environment. Key lithographic parameters, including exposure energy, focus offset, and thermal processing conditions, were systematically optimized to establish a stable and reproducible process window. Cross-sectional analysis confirmed the structural integrity of the electroplated RDL features formed under the optimized conditions. To assess functional feasibility, channel-level electrical simulations were performed using JEDEC-defined HBM3 signal assignments. Simulated eye diagrams indicate that the fabricated fine-pitch RDL interconnects are capable of supporting HBM3-class signal transmission with a moderate level of signal integrity. The presence of jitter and noise suggests that further optimization of RDL transmission line impedance is required. Rather than presenting a fully optimized interposer solution, this work provides an engineering-level assessment of lithographic and process constraints associated with implementing 2 μm class RDLs in FOWLP-based interposers, offering practical insight into fine-pitch RDL process window definition for advanced packaging applications. This work uniquely combines systematic CAR-based lithography optimization with cross-sectional structural validation and HBM3-class channel-level simulations to define a practical process window for 2 μm/2 μm RDLs in an FOWLP environment.

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Jung Won Lee www.mdpi.com